Abstract : Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds around 143 MHz. They also provide hidden precharge time and the ability to randomly change column addresses on each clock cycle during a burst cycle. This SDRAM Controller is designed to interface to standard microprocessors. The controller is independent of processor type. This design, as implemented, supports two 16MB memory regions configured as 4 M x 32 bits. Changing byte enable inputs and address inputs will change the width and size of this design. For example, if a 64-bit wide data bus is desired, increase the byte enable signals from 4 to 8. If a larger memory space is required, add address inputs and reconfigure the row and column address appropriately or add more chip selects.
Before SDRAM read and write cycles can be performed, the SDRAM sub-system must be initialized. This entails performing a precharge cycle, 2 auto refresh cycles followed by a load mode register cycle. Commands are encoded in the SDRAM signals
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