Abstract - The implementation of QR Decomposition based Recursive Least Square (QRD-RLS) Algorithm on Field Programmable Gate Arrays (FPGA). QRD-RLS is suitable for a wide variety of wireless applications and moreover the speed and flexibility of FPGAs render them viable for the computationally intensive applications. The design is based on Hardware-Software Co-design, which consists of a custom peripheral that solves the part of the algorithm with higher computational costs and embedded soft processor that manages the control functions and rest of the algorithm. The use of Givens Rotation and Systolic Arrays in QRD-RLS make this architecture suitable for FPGA implementation. The system is implemented on Xilinx Spartan3E FPGA with Microblaze soft core processor using Embedded Development Kit (EDK). The report also presents the implementation results and their analysis.

INTRODUCTION
Adaptive signal processing plays an important role in broadband wireless communications with very high signal transmission rates. A signal processor that can estimate the parameters related to the communication channels on a real time basis is indispensable in such applications. In radar applications the data rate is of the order of Megahertz and the process of calculating adaptive weights for such environments can be a very computationally demanding task. [1] QR based RLS is a well established technique for solving the least mean squares problem by calculating adaptive weights and is extensively used in applications like beam forming, Multiple Input Multiple Output (MIMO) [2]. Good numerical performance is achieved by performing the algorithm using Givens Rotation. An efficient implementation of RLS algorithm achieves much faster convergence than the least mean square algorithm; however its complexity increases in proportion to the square of the number of parameters to be estimated [3]. To overcome this problem our architecture is based on a pipelining technique referred to as systolic array. The design standards are continually evolving and this creates an element of risk for application specific integrated circuits (ASIC) implementations. Reconfigurable logic devices such as FPGAs are upgradeable and hence they reduce the risk of depending on evolving standards of industries. FPGAs have been very effective to implement computationally expensive signal processing algorithms. Moreover, FPGAs with embedded processors are flexible by nature and allow reconfiguration of logic with optimum use of resources. Over the last few years, the huge advancement in FPGA technology has made possible the implementation of whole system on single chip with processors, peripherals and memories.
The evolution of hardware-software co-design concepts has also accelerated the developments of systems on single chip [4]. Hardware-software co-design is based on an architecture that implements an embedded processor and one or more dedicated hardware coprocessors. This approach takes advantage of both the flexibility of processors and power and speed of a dedicated hardware.