The project covers the logical designs and simulation of 8-bit increment or decrement. The design includes register transfer level description code which includes both behavioral and data flow model, test bench programmers, simulation and verification by using verilog hardware description language. The 8-bit increment or Decrement or circuit functions like an adder or subtract or with one of its three inputs set to zero. The cell uses its current state as one input and carries in from the previous stage as the other input.